In the fabrication of semiconductor devices from a silicon wafer, a variety of semiconductor processing equipment and tools are utilized. One of those processing tools is used for polishing thin, flat semiconductor wafers to obtain a planarized surface. A planarized surface is highly desirable on a shadow trench isolation (STI) layer, on an inter-layer dielectric (ILD) or on an intra-metal dielectric (IMB) layer which is frequently used in memory devices. The polarization process is important since it enables the use of a high resolution lithographic process to fabricate the next level circuit. The accuracy of the high resolution lithographic process can be achieved only when the process is carried out on a substantially flat surface. The planarization process is therefore important processing step in the fabrication of semiconductor devices.
A global planarization process is often carried out using a technique known as chemical mechanical polishing. (CMP). The CMP process has been widely used on ILD or IMD layers in fabricating modern semiconductor devices. The CMP process is carried out using a rotating platen in combination with a pneumatically polishing head. The process is used primarily for polishing the front side of the device surface of a semiconductor wafer for achieving planarization and for preparation of the next level processing. A wafer is frequently planarized one or more times during a fabrication process in order for the top surface of the wafer to be as flat as possible. A wafer can be polished in a CMP apparatus by being placed on a carrier and pressed face-down on a polishing pad covered with a slurry of colloidal silica or aluminum.
A polishing pad used on a rotating platen is typically constructed in two layers overlying a platen with a resilient layer as the outer layer of the pad. The layers are often made of a polymeric material such as polyurethane and may include a filler for controlling the dimensional stability of the layers. A polishing pad is normally made several times the diameter of a wafer while the wafer is kept off-center on the pad in order to prevent a non-planar surface from being formed on the wafer. The wafer itself is also rotated during the polishing process to prevent polishing a tapered profile into the wafer surface. The axis of rotation of the wafer and the axis of rotation of the pad are deliberately off-set, however these two axes must be maintained parallel. It is known that uniformity in wafer polishing using the CMP process is a function of pressure, angular velocity and concentration of the slurry.
A CMP process is frequently used in the planarization of an ILD or IMD layer on a semiconductor device. Such layers are typically formed of a dielectric material. A most popular dielectric for such usage is silicon oxide. In the process for polishing a dielectric layer, the goal is to remove typography while maintaining good uniformity across the entire wafer. The amount of dielectric material removed is normally between about 5,000 angstroms and about 10,000 angstroms. The uniformity requirement for ILD or IMD polishing is very stringent since non-uniform dielectric films lead to poor lithography and resulting window etching or plug formation difficulties. The CMP process has also been applied to polishing metals, for example, in tungsten plug formation and embedded structures. A metal polishing process involves a polishing chemistry that is significantly different than that required for oxide polishing.
The important component required in a CMP process is an automated rotating polishing platen and a wafer holder, which of both exert a pressure on the wafer and rotate the wafer independently of the rotation of the platen. The polishing or the removal of surface layers is accomplished by a polishing slurry consisting mainly of colloidal silica suspended in de-ionized water or KOH solution. The slurry if frequently fed by an automatic slurry feeding system in order to ensure the uniform wetting of the polishing pad and the proper delivery of the recovery of the slurry. For a high volume wafer fabrication process, automated wafer loading/unloading and a cassette handler are also included in a CMP apparatus.
As the name implies, a CMP process executes a microscopic action of polishing by both chemical and mechanical means. While the exact mechanism for material removal of an oxide layer is not known, it is hypothesized that the surface layer of silicon oxide is removed by a series of chemical reactions which involve the formation of hydrogen bonds with the oxide surface of both the wafer and the slurry particles in a hydrogenation reaction; the formation of hydrogen bonds between the wafer and slurry; the formation of molecular bonds between the wafer and the slurry; and finally, the breaking of the oxide bond with the wafer or the slurry surface when the slurry particle moves away from the wafer surface. It is generally recognized that the CMP polishing process is not a mechanical abrasion process of slurry against the wafer surface.
While the CMP process provides a number of advantages over the traditional mechanical abrasion type polishing process, a serious drawback of the CMP process is the difficulty in so-called "end point" detection. The CMP process is frequently carried out without a clear signal as to when the process is complete. In the past, end point detection was largely based on determining the empirical polishing rates and time. Since the calculation of polish time required based on empirical polishing rates is frequently inaccurate, the empirical method frequently fails to accurately predict the end point, thus resulting in scrap, and significant reductions in yield. Attempts have been made to utilize an end point detection mechanism that includes capacitance measurements and optical measurements. However none of these techniques has been entirely satisfactory in achieving accurate control, of the dielectric layer removed.
Another method for achieving end point detection involves directing a laser beam onto the surface of the wafer and analyzing the light reflected from the wafer surface to determine changes in optical interference that are related to the amount of material removed. Specifically, the light reflected from a patterned wafer surface is processed by digital filtering algorithms such that the intensity of the optical interference changes periodically with the thickness of removed surface material. This technique is sometimes adequate for the detection of the end point in a polishing process wherein only a relatively thin layer of material is removed. However, when a larger amount of material is removed on a semiconductor structure such as an IMD oxide layer having a thickness of 4,000 angstroms or larger, this technique does not provide reliable results because the detection system can not distinguish which of the wave form cycles that the end point coincides with. As a result, it is possible that the wafer surface is either over-polished or under-polished by a thickness as much as 2,400 angstroms.
One of the reasons that traditional optical end point detection methods are not effective when used to detect end point near IMD layers is that there is a relatively high amount of feedback noise included in the reflected optical signal. Moreover, when multiple IMD layers are present, the reflected optical signal includes components of both IMD layers, thus making it nearly impossible to determine the current polishing thickness relative to the IMD layer that is used as a reference depth. In other words, prior art optical techniques for detecting the end point in a CMP process possesses low signal-to-noise ratios, and poor longitudinal selectivity. Accordingly, there is a clear need in the art for an improved method and apparatus for detecting an end point that exhibits a high signal-to-noise ratio and superior longitudinal selectivity that is not affected by the presence of metal compound sub-layers. The present invention is directed towards satisfying this need.